1. Field of the Invention
The present invention relates to a technique for collecting and controlling status information between a plurality of application specific integrated circuits (referred to hereinafter as ASICs) and a monitoring control unit in a communication system.
2. Description of the Related Art
In communication systems, a monitoring control unit with a microprocessor therein is adapted to collect status information from a plurality of units in a pin-to-pin manner, analyze the collected status information and perform desired control operations in accordance with the analyzed results. With semiconductor techniques being developed, ASICs have greatly been enhanced in integration degree and, in most communication systems, one or more ASICs have been employed. These make the size of systems smaller and allows only one unit to implement functions which would conventionally be implemented by many units. As a result, the limited pin-to-pin connection results in a problem in that it cannot accommodate a large amount of status information detected in the units. In order to overcome this problem, each ASIC is designed to have a central processing unit (referred to hereinafter as a CPU) interface circuit so that it can be regarded as a part of devices such as a RAM, ROM, etc. contained in the monitoring control unit.
In a status information collection/control apparatus, L ASICs of the same or different types may be contained in an arbitrary operation processing unit.
Each ASIC sends a plurality of (for example, N) status information units Sta 1-Sta N to a CPU (not shown) and receives N control information units Con 1-Con N from the CPU. The status information units Sta 1-Sta N are the results (for example, transmission line abnormal) obtained by checking specific statuses of the corresponding ASIC. The control information units Con 1-Con N are the control contents of the CPU regarding the status information units Sta 1-Sta N. Although not shown, each of the ASICs may be connected to other internal circuits or other external boards (or units). A select signal generator 50 receives a unit select signal SEL which is generated by the CPU to select a specific unit (or chip) and an address ADD, and generates ASIC select signals CS 1-CS L of desired states to select the corresponding chips, or ASICs. The address ADD is generated by the CPU to address a memory included in a CPU interface circuit in the ASIC. In addition, a write enable signal WE is applied to the ASICs to write control data into the memory in the CPU interface circuit in the ASIC. A read enable signal RE is applied to the ASICs to read status information from the memory in the CPU interface circuit in each ASIC. A data bus DB is a bidirectional data communication path between the CPU and the ASICs, for transferring the status information from the ASICs to the CPU and the control information from the CPU to the ASICs.
However, the above-mentioned status information collection/control apparatus has four problems as follows.
Firstly, the CPU interface circuit is very complex in construction because it includes a decoding circuit, multiplexing circuit, latch circuit and various combination logic circuits. Also, with unused memory area becoming larger, more unnecessary gates are used. In other words, if such complex circuits are contained in the respective ASICs and such ASICs are large in number, the use of unnecessary gates will be increased.
Secondly, the CPU interface circuit requires a large number of internal patterns (for example, pin arrangements). In the case where each ASIC is designed with a field programmable gate array (FPGA), the larger number of signal patterns makes the routing of the FPGA more difficult, resulting in a degradation in performance of the ASIC.
Thirdly, all of the ASICs must have address buses of the same size and data buses of the same size regardless of the number of their status information units. If status and control information units to be processed in each ASIC are smaller in number, namely, if N is smaller, unnecessary pins in each ASIC will become larger in number. The larger number of unnecessary pins increases the cost of each ASIC.
Fourthly, the processor must read or control all ASICs contained in one unit in response to one unit select signal SEL. Namely, the ASIC select signals CS 1-CS L are produced by combining the unit select signal SEL with a signal obtained by decoding a portion of high-order bits of the address. This requires a separate circuit. If this separate circuit is designed with a common logic IC, it will occupy a large amount of space in the unit and reduce the reliability of the unit.
The following patents each discloses features in common with the present invention but do not teach or suggest the specifically recited status information collection/control arrangement for a communication system of the present invention: U.S. Pat. No. 5,233,612 to Huyskens et al., entitled Test Device for An Electronic Chip, U.S. Pat. No. 5,163,052 to Evans et al., entitled High Reliability Computer Diagnostics System, U.S. Pat. No. 5,432,464 to Damault, entitled Application Specific Integrated Circuit Including A Microprocessor For Customized Functions As Defined By The User, U.S. Pat. No. 5,615,335 to Onffroy et al., entitled Storage System Self-Test Apparatus And Method, U.S. Pat. No. 5,710,934 to Bona et al., entitled Methods And Test Platforms For Developing AN Application-Specific Integrated Circuit, U.S. Pat. No. 5,802,270 to Ko et al., entitled Integrated Circuit Having AN Embedded Digital Signal Processor And Externally Testable Signal Paths, U.S. Pat. No. 5,774,708 to Klingler, entitled Method To Test The Running Of A Program Of Instructions Carried Out By An ASIC And ASIC Pertaining Thereto, U.S. Pat. No. 5,764,952 to Hill, entitled Diagnostic System Including ALSI Or VLSI Integrated Circuit With A Diagnostic Data Port, U.S. Pat. No. 5,423,050 to Taylor et al., entitled Intermodule Test Across System Bus Utilizing Serial Test Bus, U.S. Pat. No. 5,005,172 to Kawamoto, entitled Diagnostic System In A Data Processing System, U.S. Pat. No. 5,754,759 to Clarke et al., entitled Testing And Monitoring Of Programmed Devices, U.S. Pat. No. 5,649,094 to Hayashi et al., entitled Self-Service Diagnostic Unit For Plural Functional Devices, U.S. Pat. No. 5,600,788 to Lofgren et al., entitled Digital Test And Maintenance Architecture, and U.S. Pat. No. 5,479,649 to Runaldue et al., entitled Method And Apparatus For Forming A logical Combination Of Signals From Diagnostic Nodes In AN IC Chip For Passive Observation At A Dedicated Diagnostic Pin.